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AMD-640 chipset i/o model document #: 21340 rev. a amendment/0 issue date: april 1997 this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. application note AMD-640? chipset i/o model introduction advances in semiconductor process technology have allowed the performance of integrated circuits to increase dramatically. the operating frequency of output signals driven from these circuits continues to increase, while the switching transitions of these signals has decreased. these particular characteristics of high-speed signals pose challenges to a system designer responsible for the placement and routing of components on printed circuit boards (pcbs). in particular, the propagation delay of a signal must be considered to ensure that sufficient setup and hold time, with adequate margin, exist at a signals destination . in addition, as the rise and fall times of signals decrease, the system designer must ensure the signal quality meets the system requirements. ensuring that system timing and signal quality objectives are met prior to pcb manufacturing reduces the development expense and expedites the time-to-market of a product. this application note describes the format and usage of the AMD-640 chipset i/o buffer behavioral model, which allows a system designer to perform analog simulations of chipset signals that interface with the system logic. this model adheres to the i/o buffer information specification (ibis), version 2.1 .
2 AMD-640 chipset i/o model 21340a/0april 1997 ibis modeling overview ibis is a specification developed to provide an industry-standard method for semiconductor manufacturers to model the analog behavior of i/o buffers without disclosing proprietary process data. as the availability of ibis models has grown, so too have the number of analog simulators that accept ibis models. ibis usage modeling a pcb net to simulate the analog behavior of a signal on a pcb net, all elements of the net must be modeled to ensure the simulator generates accurate results. a net that is driven by a signal that has a short switching transition relative to its propagation delay is best modeled as a transmission line. the general criterion used for deciding on a transmission line as an appropriate model is as follows: t switch < 2(t prop ) where: n t switch is the time required for a signal to switch states n t prop is the time required for a signal to propagate from its source to its destination the typical elements of a net sourced by the chipset include the chipsets i/o buffer (modeled using ibis), the transmission line that models the pcb trace, the destination receiver(s), and any components used for termination (see figure 1). this net topology is then defined in the format understood by the target simulator.
3 21340a/0april 1997 AMD-640 chipset i/o model figure 1. modeling example of typical pcb net after the simulator has loaded the net input file, the simulator can be instructed to generate a rising or falling transition at the driver input to the chipset driver (point a in figure 1). this signal generator is represented in figure 1 by the voltage source input to the chipset driver. setup and hold times for each signal transition, the simulator can determine the signal propagation delay from point a to point b under worst-case, typical, and best-case conditions. the propagation delay under worst-case conditions is used to determine if the setup time at the destination receiver is met. likewise, the progagation delay under best-case conditions is used to determine if the hold time at the destination receiver is met. figure 2 illustrates the timings that must be considered when determining whether the setup time of a signal is met. the timings are defined as follows: n t period is the period of the system clock n t skew is the maximum clock skew between the clock that launches a signal (solid-line clock) and the clock that captures a signal (dashed-line clock) n t jitter (not shown in figure 2) is the maximum variance allowance between successive periods of the system clock + C v cc r 1 r 2 a b AMD-640 chipset system logic pcb trace driver receiver z o voltage source
4 AMD-640 chipset i/o model 21340a/0april 1997 n t validmax is the maximum valid delay of a signal from its source n t propmax is the maximum propagation delay of the signal along the pcb trace from its source to its destination. this delay is obtained by simulating with the worst-case conditions. n t setupmin is the minimum required setup time of a signal at its destination figure 2. timing considerations for meeting setup time to ensure the setup time of a signal is met, the following relationship must be met: t validmax + t propmax + t setupmin < t period C t skew C t jitter signal at destination signal at source clocks t period t skew t validmax t propmax t setupmin
5 21340a/0april 1997 AMD-640 chipset i/o model figure 3 illustrates the timings that must be considered when determining whether the hold time of a signal is met. the timings are defined as follows: n t period is the period of the system clock n t skew is the maximum clock skew between the clock that launches a signal (solid-line clock) and the clock that captures a signal (dashed-line clock) n t jitter (not shown in figure 3) is the maximum variance allowance between successive periods of the system clock n t validmin is the minimum valid delay of a signal from its source n t propmin is the minimum propagation delay of the signal along the pcb trace from its source to its destination. this delay is obtained by simulating with the best-case conditions. n t holdmin is the minimum required hold time of a signal at its destination figure 3. timing considerations to meet hold time signal at destination signal at source clocks t period t skew t propmin t validmin t holdmin
6 AMD-640 chipset i/o model 21340a/0april 1997 to ensure the hold time of a signal is met, the following relationship must be met: t validmin + t propmin - t skew - t jitter < t holdmin signal quality in addition to providing propagation delays, the simulator can graphically display the input waveform presented at the input of the driver and the corresponding waveform produced at point b in figure 1. this display allows a designer to determine if the signal quality at the destination is acceptable. in addition to providing graphical data, most simulators generate numerical data that quantifies various signal quality characteristics. the following list shows the signal quality characteristics that typically concern designers (all measurements are taken at the destination receiver): n overshoot the difference between the maximum value of the voltage of a rising signal and the nominal i/o v cc voltage (see figure 4). overshoot can adversely affect the reliability of the destination receiver. the time during which a signal remains above the nominal i/o v cc voltage is also a reliability factor. n undershoot the difference between the minimum value of the voltage of a falling signal and ground (see figure 5). as with overshoot, undershoot can adversely affect the reliability of the destination receiver. n ringback in the case of a rising waveform, the difference between the nominal i/o v cc voltage and the minimum voltage of a signal after that signal has reached its maximum value. in the case of a falling waveform, ringback is the difference between the maximum voltage of a signal after that signal has reached its minimum value and ground (see figures 4 and 5). excessive ringing can cause the destination receiver to falsely switch if the signal traverses the switching threshold of the receiver. n ring settling time in the case of a rising waveform, the time between when a signal crosses one-half of the nominal v cc i/o voltage and when the signal settles within the specified tolerance of the i/o v cc voltage. in the case of a falling waveform, ring settling time is the time between when a signal crosses one-half of the nominal i/o v cc voltage and when the signal settles within a specific
7 21340a/0april 1997 AMD-640 chipset i/o model percentage above and below ground (the percentage is dependent upon the electrical characteristics of the destination receiver). see figure 6 for an example of ring settling time for a rising waveform. settling time that approaches the period of the clock that launches a signal can potentially increase the switching time of that signal. this increase occurs if the signal is advancing in the opposite direction of the signal transition that occurs on the next clock edge. figure 4. example of overshoot figure 5. example of undershoot overshoot time ringback v cc time undershoot ringback v cc
8 AMD-640 chipset i/o model 21340a/0april 1997 figure 6. example of ring settling time for rising waveform ibis structure the ibis specification defines a template that describes the properties of most elements of an i/o buffer design. the template uses required keywords and sub-parameters as well as optional keywords. the keywords and sub-parameters used by the AMD-640 chipset ibis model, along with their definitions, are as follows: n ibis ver specifies the version of the ibis model. n file name specifies the name of the file that contains the model. n file rev specifies the revision of the ibis model. n date specifies the date the ibis model was last modified. n copyright the copyright claim. n component specifies the name of the component the model represents. n manufacturer specifies the manufacturer of the component. n package (r_pkg, l_pkg, c_pkg)specifies the r/l/c values of the package. these values are specified as 0 because the package r/l/c values are accounted for in the r_pin, l_pin, and c_pin sub-parameters of the pin keyword. n pin (signal_name, model_name, r_pin, l_pin, c_pin, c_comp)itemizes each physical pin number along with its signal name, its i/o buffer name, and its r/l/c values. time v cc ?(v cc ) v cc tolerance settling time
9 21340a/0april 1997 AMD-640 chipset i/o model power, ground, and no-connect pins do not have r/l/c values specified. n model (model_type, vinl, vinh, vmeas, cref, rref, vref) specifies the type of i/o buffer. in the model i/o, vinl equals 0.8v, vinh equals 2.0v, and vmeas = 1.5v. cref, rref, and vref, which represent the test load under which the specified propagation delays and switching times are defined, equal 0. c_comp specifies the capacitance of the silicon die. n temperature range specifies the temperature range within which the operation of the component is guaranteed. n voltage range specifies the i/o voltage range. n pulldown specifies the voltage versus current (v/i) curves of the pulldown device within the i/o buffer. n pullup specifies the v/i curves of the pullup device within the i/o buffer. n gnd clamp specifies the v/i curves of the ground clamp device within the i/o buffer. n power clamp specifies the v/i curves of the power clamp device within the i/o buffer. n ramp (dv/dt_r, dv/dt_f, r_load)specifies the rise and fall times of a signal at a load defined by r_load. r_load is equal to 50 ohms. n rising waveform specifies the voltage versus time (v/t) curves of the rising edge of the waveform. n falling waveform specifies the v/t curves of the falling edge of the waveform.
10 AMD-640 chipset i/o model 21340a/0april 1997 ibis models amd provides models of the AMD-640 system controller and the amd-645? peripheral bus controller i/o buffers for system designers to use in board-level simulations. these i/o buffer models conform to the i/o buffer information specification (ibis), version 2.1 . i/o buffer models represent the characteristics of the drive strength configuration supported by the AMD-640 chipset. the model also associates the appropriate driver type to its respective pin. in the AMD-640 system controller, the memory drivers are programmable by configuration registers. hence the designer must select the 12ma or 24ma driver, depending on the intended use. each i/o model contains voltage versus current (v/i) and voltage versus time (v/t) data tables for accurate modeling of i/o buffer behavior. the following list summarizes the properties of each i/o buffer model: n all data tables contain minimum, typical, and maximum values to allow for worst-case, typical, and best-case simulations, respectively. n the pullup, pulldown, power clamp, and ground clamp device v/i tables contain enough data points to accurately represent the nonlinear nature of the v/i curves. in addition, the voltage ranges provided in these tables extend beyond the normal operating range of the AMD-640 chipset for those simulators that yield more accurate results based on this wider range. n rising and falling ramp rates are specified. n the min/typ/max v cc3 operating range is specified as 3.135 v, 3.3 v, and 3.465 v, respectively. n v il = 0.8 v, v ih = 2.0 v, and v meas = 1.5 v. n the r/l/c of the package is modeled. n the capacitance of the silicon die is modeled. n the model assumes 0 capacitance, resistance, inductance, and voltage in the test load.
11 21340a/0april 1997 AMD-640 chipset i/o model standard i/o model the standard i/o model is available from the amd web site at http://www.amd.com . trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. AMD-640 and amd-645 are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
12 AMD-640 chipset i/o model 21340a/0april 1997

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